Apparatus for detecting traffic delay



1970 SHUNSUKE IWAMOTO ETALI ,53

APPARATUS FOR DETECTING TRAFFIC DELAY Filed Oct. 16, 1967 Y 2 Sheets-- heet 1 FIG. 1.

A v \V// f t/' 74;/ 4 I r PULSE NUMBER TIME i k w/W ATTORNEYS 1970 SHUNSUKEI IWAMOTO ETAL ,53

APPARATUS FOR DETECTING TRAFFIC DELAY Filed Oct. 16, 1967 2 Sheets-Sheet 2 N MRI: 1

INVENTORS Sfluusulfli rum/0T0 #1500 WITIWIHE BY mild/I films/9% (7 ATTORNEYS United States Patent T Japan Filed Oct. 16, 1967, Ser. No. 675,412 Claims priority, application Japan, Oct. 20, 1966, 41/ 69,344 Int. Cl. G08g 1/01 US. Cl. 235-15024 6 Claims ABSTRACT OF THE DISCLOSURE An apparatus for determining trafiic delay by measuring a quantity proportional to the density of vehicular traffic in a zone of a street plus the percentage of time that zone is occupied by vehicles. A vehicle detector placed in each lane of the street produces an electrical signal as long as a vehicle is within the lane zone. Each of these electrical signals is then converted into a pulse train whose length is determined by the duration of the signal. The pulse trains are summed and passed through a series of dividers which have a selectively variable division factor to obtain a usable, composite pulse train. This composite pulse train is then further divided by the number of lanes to obtain a single pulse train representative of the average count per lane. The single train is applied to a settable counter which produces a plurality of outputs for predetermined pulse counts. These outputs are temporarily stored in a first set of flip-flops, then transferred to a second set of flip-flops under control of a gating circuit after a known, predetermined time interval, and the counters are reset whereby measurement may be made for another time interval. The contents of the second set of flip-flops thus represents a rough approximation to the desired quantity of traflic delay. 7

This invention relates to an apparatus for detecting trafiic delay or stagnation on streets.

In order to know the traffic condition on a street, it is necessary to detect the degree of traffic stagnation or delay on the street. In order to detect the traflic delay or stagnation it has hitherto been customary to rely on eyemeasurement of the traflic condition or to use a traffic volume detector. The traflic volume is defined as the number of vehicles passing a point on a street during a predetermined period of time. Practically, however, the trafiic volume does not always give us a correct and exact information about the actual traflic condition on the street. For example, as traffic delay increases, the speed of vehicles decreases, with resulting decrease in the traffic volume. If traffic has been substantially stopped, the trafiic volume becomes zero. On the contrary, if there is no traffic at all, the traffic volume is also zero. Therefore, in order to correctly know the traflic delay on a street, some other factors or information than trafiic volume are required. Theoretically, such other factors are traflic density, space occupancy, time occupancy, etc. Here, the tratlic density is defined as the number of vehicles existing Within a predetermined length of a street at a predetermined time; the space occupancy, as the ratio of the sum of the lengths of all the vehicles existing within a predetermined length of a street at a predetermined time, to that predetermined length of the street; and the time occupancy, as the ratio of the sum of the periods of time of existence of vehicles at a point on a street during a predetermined period of time, to this period of time.

3,536,900 Patented Oct. 27, 1970 Although these factors or informations may give us a substantially exact and correct recognition of the trafiic condition on the street, there has been proposed, to the best knowledge of the present inventors, no apparatus that gives us such information in a form ready to be utilized for various purposes of traffic control.

Accordingly, the primary object of the invention is to obtain an information consisting of traflic density and time occupancy, which enables us to instantly know the degree of the trafiic delay or stagnation on a street.

Another object of the invention is to provide a simple method of obtaining such an information as aforesaid.

Still another object of the invention is to provide a simple apparatus for obtaining such an information as aforesaid.

The invention employs a vehicle detector which is placed at a predetermined point on a street and so adapted as to continue an output so long as a vehicle is in the field of the detector. The detector may be called the presence type of vehicle detector. In accordance with the invention, all the periods of time during which the detector output continues within a predetermined unit period of time are summed up, and the ratio of the sum to that unit period of time is calculated. The ratio is a function of the traflic density and time occupancy on the street and presents a value proportional to the traflic delay or stagnation thereon. Therefore, the value can be utilized as an information on the basis of which trafiic control most suitable for the traflic condition may be performed, or which may be published for drivers to know the traflic condition on the street.

The invention will be clearly understood from the following detailed description of a preferred embodiment thereof with reference to the accompanying drawings, wherein:

FIG. 1 is a schematic side view showing the relative position of a vehicle detector and vehicles;

FIG. 2 is a schematic perspective view of a street with a vehicle detector installed therein;

FIG. 3 is a detailed circuit diagram of the apparatus of the invention; and FIG. 4 is a graph illustrating the lines expressing four different degrees of traflic delay by diiferent numbers of pulses produced by the system during a predetermined period of time.

Referring to FIGS. 1 and 2, there is shown a vehicle detector 10 embedded in the surface of a street 12 and comprising a loop coil 14 and an oscillator 16. The loop 14 may either be the oscillating coil itself of the oscillator 16 or part of it. When a vehicle 18 passes the coil 14, the oscillating condition of the oscillator 16 changes so that it produces a continuous output. The arrangement is such that as shown in FIG. 1, when a vehicle 18 approaching in the direction of an arrow 20' comes to overlap the loop 14 to a predetermined extent, the oscillator 16 produces an output which continues until the vehicle advances so that the overlapping of the vehicle 18 and the loop 14 decreases to less than a predetermined length, whereupon the oscillating output stops. To put it in more concrete terms, let it be assumed that the opposite sides of the loop 14 at right angles to the direction of the vehicle movement be indicated by A and B, respectively. When the vehicle enters the loop 14 and arrives at a point spaced a distance S1 from the side A thereof, the oscillator 16 starts its oscillation, which continues until the rear end of the vehicle passes a point spaced a distance S2 in front of the opposite side B of the loop 14.

The oscillating output from the oscillator 16 is applied through various relays and circuits, not shown, with resulting time delay, to a calculating circuit 21 to be described hereinafter. Let the time delay caused when the vehicle enters the loop 14 be expressed by t the time delay caused when it leaves the loop 14, by t and the speed of the vehicle, by v. Then, the distance that the vehicles advances from the time when the oscillator output started to the time when this oscillator output enters the calculating circuit 21 can be expressed by W and the distance that the vehicle advances from the time when the oscillator output disappeared to the time when that output being applied to the calculating circuit 21 disappears can be expressed by vt If the vehicle keeps its speed constant while it passes the loop 14, and if the delay times t and t can be considered substantially equal, the distances vt and vi are substantially equal. Therefore, the output from the oscillator 16 continues while the vehicle is passing the detector range D within the loop 14. Here, if the width of the loop, that is, the distance between the opposite sides A and B thereof, is W, the detector range D can be expressed by D=W(S +S and the value D is constant since W, S and S are all constant. In practice, the values S and S are variable with different vehicles, but such variation is practically negligible.

The period of time If during which the running vehicle exists within the detector range D can be expressed by where L is the overall length of the vehicle and v is the speed of the vehicle. The detector output lasts for this period of time t.

Suppose that the number of vehicles that have passed the loop 14 during a predetermined period of time T is n; that the speed of each of these vehicles is v where i=1, 2, 3 n; and that the overall length of each of the vehicles is L, where i=1, 2, 3 n. The sum of the periods of time during which the detector outputs caused by all the vehicles exist within the period of time T will be expressed as follows:

n D+L ET. i=1 1 And the ratio R of the above sum to the unit period of time T will be expressed as:

D-i-L,

In accordance with the invention the value R is used as an information by which to recognize the trafiic delay or stagnation on the street. In practice the value R can be easily obtained by, for example, summing the outputs of the detector produced during the period of time T and then dividing the resultant sum by the period of time T. This calculation can be performed by the circuit 21 to be described hereinafter.

As previously mentioned, the information by which to recognize the degree of traffic delay or stagnation on a street consists of traffic density and time occupancy. If the above-mentioned value R is a function of these factors and varies in proportion to the degree of traflic delay or stagnation, the value R can be relied on as an indication of the degree of traffic delay or stagnation.

The Equation 1 can be rewritten as:

As previously mentioned, the traffic volume Q is the number n of vehicles passing a point on a street during a predetermined period of time T and can be expressed as:

On the other hand, the space mean speed V which is defined as the average speed of all the vehicles running Within a predetermined zone of a street at a given time, can be approximately obtained from the following Equa tion 4 by measuring the speed v (i=1, 2, 3 n) of 4 the vehicles (the number of which is n) passing a point on the street during a predetermined period of time T.

1 n 1 V E Also, it is well known that the relation between the space mean speed V the traffic volume Q and the traflic density K can be expresed by the following equation:

K- v. Substituting the Equations 3 and 4 into 5 gives:

n l v 1 1'1 1 K= 1 T n T v, (6)

Let the above Equation 6 be substituted into the first number of the Equation 2, and the first number, that is,

n 2 i i=1 If the predetermined period of time is expressed as T, the time occupancy O will be given as:

On the other hand, the period of time P, during which a vehicle occupies a point within the range D of the loop 14 is given as L /v, where L, is the length of the vehicle and v the speed thereof. Then, if the periods of time of all the vehicles that have occupied the point are summed up, the result will be i=1 vi The expression is nothing but the expression of n 2 Pi i=1 in the Equation 7. Thus, the second number of the Equation 2 can be expressed simply as 0,,, so that This Equation 8 shows that the value R is a function of traflic density and time occupancy and, consequently, it can indicate the traflic condition on the street in the following manner. For example, if trafiic is flowing smoothly with long headway, the density K is kept at a low level, with a low value of time occupancy. However, as traflic is becoming delayed, the density K increases in proportion to the traffic delay and, consequently, the vehicle speed decreases, so that the time period during which each vehicle occupies a point on the street becomes longer, with resulting increase in the value 0,,. This means that the value R becomes greater and greater as traffic delay increases. The value R can be utilized to inform drivers of the trafiic condition on the road, or on control the signal indications, offset, signal cycle, etc. at various street intersections for a smoother trafiic How on the street.

The circuit 21 for calculating the value R may be of any suitable type. For example, it may be such that the output pulses from the vehicle detector are summed for a predetermined period of time T, or such that clock pulses are counted during the period of time when the detector output continues, so that the total number of pulses counted during the period of time T is considered as the value R.

FIG. 3 shows an arrangement employing pulse counters in the calculating circuit 21. The circuit of FIG. 3 is designed for a street having a plurality, say, a maximum of five lanes. A pulse generator 22 produces a series of clock pulses, which are counted by a pulse counter 24. The cycle of the clock pulses may be determined by the maximum speed of vehicles expected to pass the detector 14. In practice, preferably it is about 2 or more kHz.

There are provided five input terminals 25 through 29, so that a maximum of five lanes for a street can be measured. A desired one or more of the input terminals may be used, depending upon the number of lanes of the street to be measured. If, for example, the street has two lanes, one vehicle detector is installed in each of the two lanes, and the output from one of the two detectors is connected to a desired one of the input terminals 25 though 29 while the output from the other detector is connected to another of the input terminals.

A switch 31 has its movable arm 32 selectively connectable to the five output terminals 1 to 5 of a pulse counter 30, depending upon the number of those of the input terminals 25 to 29 that are used, or the number of lanes to be measured. In FIG. 3, the switch arm 32 is shown connected to the terminal 5 of the counter so as to measure five lanes. If two lanes are to be measured, the arm 32 will be connected to the output terminal 2 of the counter, as will be easily understood. The function of the counter 30 and the switch 31 will be referred to in detail later.

Five diode AND circuits comprises the output terminals 0, 2, 4, 6 and 8 of the counter 24 connected to the five input terminals 25 to 29 through diodes 33 to 37, respectively, so that the outputs from the counter 24 can scan the input terminals 25 through 29. It will be easily seen that when the output at any of the output terminals of the counter 24 coincides with the input at the corresponding one of the input terminals 25-29, an output is produced by that diode AND circuit. The outputs from these diode AND circuits are applied to an OR element 38.

Suppose that an input is being applied to the terminal 25. During that period of time, every time the counter 24 produces an output at its terminal, the uppermost diode AND circuit produces an output to be applied to the OR element 38. If the frequency of the output pulses from the generator 22 is 2 kHz., the cycle of the pulses at each output terminal of the counter 24 is second. ,Suppose that the speed of the vehicle is 40 kilometers per hour; its length, 4 meters; and the detector range D, 1 meter. Then, the inut applied to the terminal 25 lasts 450 milliseconds. During this period of time, that is, until the vehicle has passed the detector range, 90 pulses are produced from the OR element 38.

The value R can be obtained by counting the number of the input pulses to the OR element 38 (or the output pulses therefrom) for a predetermined period of time T, for example, one minute, and then dividing the counted number by the number of the lanes being measured. To this end, the output pulses from the OR element 38 are applied to a quaternary counter 40, the carry output pulses from which are applied to a decimal counter 41. The carry pulses from the counter 41 are in turn applied to a second quaternary counter 42. Since the cycle of the output pulses at each output terminal of the counter 24 is milliseconds, the OR element 38 produces one output pulse per 5 milliseconds during the period of time when only one of the terminals 25 to 29 is receiving an input. If two or more of the terminals 25 to 29 are receiving an input, the OR element 38 produces 6 the same number of pulses per 5 milliseconds as the number of the terminals receiving an input.

Suppose that one of the input terminals 2529 is receiving an input. The quaternary counter 40 produces one output pulse for every 20 milliseconds. The counter 41 and 42 may be combined into a single counter circuit 43, which normally would produce one output pulse for every 30 input pulses applied to the counter 41. However, trafiic conditions sometimes require the counter 43 to function otherwise. For example, when there is very little trafiic on the street, the sum of the periods of time during which the detector outputs exist within a predetermined period of time becomes so short that the number of output pulses produced from the OR element 38 within the predetermined period of time decreases to make it practically impossible to perform measurement.

To solve this problem and increase the number of pulses from the counter circuit 43, a switching circuit 47 is provided, which comprises a selector switch 47 and a plurality of diode AND circuits. The switch 47 has its movable contact arm 49 connected to a source 48 on the one hand and selectively connectable to the terminals 50 to 54 of the diode AND circuits. When the arm 49 is in contact with the terminal 50, the counter 43 functions normally due to the connections of diodes 55 and 56 to the 0 and 3 output terminals of the counters 41 and 42, respectively, that is, the counter 43 applies one output pulse to an OR element 57 for every 30 input pulses received from the counter 40. When the arm 49 is switched over to the terminal 51, the counter 43 applies one pulse to the OR element 57 for every 20 input pulses received, due to the connections of diodes 58 and 59 to the output terminals 0 and 2 of the counters 41 and 42, respectively. In this case, the cycle of the output pulses from the OR element 57 is two-thirds of that in the previous case. When the switch arm 49 is connected to the terminals 52, 53 and 54, respectively, the counter 43 applies one pulse to the OR element 57 for every 15, 12 and 10 input pulses received, respectively, due to the connections of diodes 60 and 61, 62 and 63, and 64 and 65 to the output terminals of the counters 41 and 42. In these cases, the cycles of the output pulses from the OR element 57 are one-half, two-fifths, and one-third, respectively, of the cycle in the first case in which the counter circuit functions normally.

The output from the OR element 57 triggers a one-shot multivibrator 66, the output from which is in turn ap plied to an amplifier 67. The amplified output is applied as a reset signal to the counters 41 and 42 on the one hand and as input pulses to the counter 30 on the other.

Mention has already been made that the arm 32 of the switch 31 is connected to that one of the output terminals of the counter 30 which corresponds to the number of those of the input terminals 2529 which are used. Suppose, for example, that two of the five terminals 25-29 are used. The OR element 38 receives a maximum of two pulses for every one counting cycle of the counter 24. Therefore, if the number of the output pulses from the counter 43 is divided by the number of the lanes being measured, the average number for each lane can be obtained. This dividing operation is performed by the counter 30 and the selector switch 31, whose arm 32 may be connected, in the present case, to the output terminal '2 of the counter 30.

When five lanes are being measured, the arm 32 is in contact with the 5 output terminal of the counter 30. In this case, every five input pulses to the counter 30 produces one output at the 5 terminal thereof. This means that the number of output pulses from the counter 43 is now divided by 5.

The output pulses from the counter 30 are applied through the switch arm 32 to trigger a one-shot multivibrator 70, the output from which is applied to an amplifier 71. The amplified output is applied as a reset signal back to the counter 30 on the one hand and to a decimal counter 72 on the other. This counter 72 is combined with a second decimal counter 73 and a binary counter 74 to constitute a counter circuit 75 for the purpose to be described below. It will be easily seen that the counting capacity of the circuit 75 is 200 pulses in one counting cycle.

Three pinboards 76, 77 and 78 are connected to the output terminals of the three counters 72 to 74. To each of the pinboards is connected a diode AND circuit, which is connected to a source terminal 88 and also to the output terminals of the counters 72, 73 and 74 through pinholes. The diodes are designated by 79, 80 and 81 in the uppermost pinboard 76, by 82, 83 and 84 in the intermediate pinboard 77, and by 85, 86 and 87 in the lowest pinboard 78.

The outputs from the diode AND circuits 76 to 78 are applied as a set input to flip-flops 90, 91 and 92, respectively. The set and reset outputs from the flip-flops to 92 are applied as one input to a diode AND circuit 93, to the other input of which a suitable source, not shown, applies timing pulses through a terminal 94 and an amplifier 95 in a predetermined cycle (corresponding to the previously mentioned period of time T). The outputs from the diode AND circuit 93 are applied as set and reset inputs to flip-flops 96 through 98. The timing pulses applied to the terminal 94 are also applied through an amplifier 99 to the counters 72, 73 and 74 to reset them in the predetermined cycle. The reset inputs to the flipflops 90 to 92 are supplied from a terminal 100, to which are applied pulses in the same cycle as that of the pulses at the terminal 94, but a little later than the latter pulses.

Suppose that in the three pinboards 76, 77 and 78, a pin is inserted in each of those pinholes which are shown hatched in FIG. 3. When the counter 30 has applied 50 pulses to the counter 72, the flip-flop 90 is set to produce a set output, When the counter 30 has applied 50 more pulses (that is, 100 pulses from the first), the flip-flop 91 is set. When the counter 30 has applied 50 more pulses (that is, pulses from the start), the flip-flop 92 is set.

On the other hand, when a timing pulse has been applied to the terminal 94 in the cycle T, it resets the counters 72, 73 and 74 on the one hand and is applied as an input to the diode AND circuit 93 on the other, so that the outputs from the diode AND circuit 93 sets or resets the flip-flops 96 to 98, depending upon the output conditions of the flip-flops 9092. That is, if the flip-flop 90 is in a set condition, the flip-flop 96 is set and if the flip-flops 91 and 92 are in a set condition, the flip-flops 97 and 98 are set. Thus, the conditions of the flip-flops 90-92 are transferred to the flip-flops 96-98, respectively. A fraction of time after the application of an input to the terminal 94, a pulse is applied to the terminal 100, so that the flipflops 90-92 are all reset. The set outputs of these flip-flops appear at the terminals 101-103, respectively.

The number of pulses applied to the counter 72 expresses the average of the time periods during which inputs exist at those of the terminals 2529 which are in use, that is, the average of the time periods during which the detectors 10 in the corresponding lanes are detecting vehicles. In other words, according to the invention, the number of pulses applied to the counter 72 during the period of time T expresses the value R.

Also, it will be seen that it is possible to classify the degrees of trafiic delay on the street by knowing which of the flip-flops 96-98 produces a set output during the period of time T. In the graph of FIG. 4, wherein time is taken along the abscissa and the pulse number along the ordinate, the pulse number increases as time goes on. At the end of the period of time T, if the pulse number is less than 50 as shown by line A so that none of the flip-flops 96-98 are set, the degree of trafiic delay may be classified as Degree I. If the pulse number is more than 50 inclusive but less than 100 as shown by line B so that the flip-flop 96 only is set, the degree may be classified as Degree 11; if the pulse number is more than 100 inclusive but less than 150 as shown by line C so that flip-flops 96 and 97 are set, the degree may be classified as Degree III; and finally if the pulse number is more than 150 inclusive but less than 200 as shown by line D so that all the three flip-flops 96-98 are set, the degree of delay is most aggravated and classified as Degree IV. It will be apparent that such classified indication of the difierent degrees of trafiic delay will be very convenient in trafiic information services and control.

Having illustrated and described one preferred embodiment of the invention, it is understood that the invention is by no means limited thereto, but that there may be many changes and modifications within the scope of the invention as defined in the appended claims. For example, the counters 43 and 30 are interchangeable in position in the network, with necessary changes in the associated circuit connections. Also, for a single lane, the counter 24 may be eliminated and instead, a diode AND circuit may be formed to receive the outputs from a single detector on the lane and those from the pulse generator 24.

What We claim is:

1. An apparatus for detecting the traflic delay on a street which has a plurality of traific lanes, comprising:

(a) a plurality of vehicle detectors, one provided for each of said lanes and each detector operable in response to each vehicle passing a defined portion of said lane, said portion extending in the direction of vehicle travel, to produce an output which continues for the period of time during which said vehicle is present within said defined portion,

(b) means for scanning said detectors so as to produce a first signal when said detectors produce outputs,

(0) means for dividing said first signal by the number of said lanes to produce a second signal,

((1) means for summing, during a predetermined period of time, the periods of time during which said second signal from said dividing means is present, and

(e) means for producing an output signal corresponding to the resultant sum.

2. The apparatus as recited in claim 1, further including a plurality of memory elements for memorizing the output from said summing means after said predetermined period of time has elapsed.

3. An apparatus for detecting the traffic delay on a street which has a plurality of traffic lanes, comprising:

(a) a plurality of vehicle detectors, each for one lane,

(b) a pulse generator for producing a series of timing pulses in a predetermined cycle,

(c) a pulse counter for counting said timing pulses to produce scanning pulses (d) means operable upon coincidence of said scanning pulses and the outputs from said detectors to produce output pulses,

(e) means for dividing said output pulses from said coincidence means by the number of said trafiic lanes,

(f) digital counter means for counting said output pulses produced by said dividing means during said period of time, and

(g) means producing an output corresponding to the resultant count.

4. The apparatus as recited in claim 3, wherein said dividing means comprises a second digital counter counting said output pulses, and further including means for resetting said second digital counter upon each output pulse from said dividing means.

5. The apparatus as recited in claim 3, further including a count-setting means connected to said first digital counter means and operative to provide a plurality of distinct outputs upon the count in said first digital counter means reaching a plurality of distinct values, and wherein said means producing an output corresponding to the resultant count comprises a plurality of memory elements for memorizing said plurality of distinct outputs of said count-setting means after said predetermined period of time has elapsed.

6. The apparatus as recited in claim 5, further comprising:

(a) means resetting said first digital counter means after said predetermined period of time has elapsed,

(b) a second plurality of memory elements for memorizing the contents of said first plurality of memory elements,

(c) means for transferring the contents of said first plurality of memory elements to said second plurality of memory elements at intervals equal to said predetermined time period, and

(d) means clearing said first plurality of memory elements a short time after the transfer of the contents thereof to said second plurality of memory elements.

References Cited UNITED STATES PATENTS 4/1952 Barker et a1 23592 4/1967 Auer 235--l50.24 8/1968 Auer 235-15024 8/1968 Auer 235-15024 10/1968 Zupznick 34038 X US. Cl. X.R. 

